A significant improvement in the energy efficiency of digital technology is required to enable further progress in information systems in the wake of considerable scaling challenges facing conventional CMOS [1]. Superconducting single flux quantum (SFQ) technology is capable of very low power dissipation and high speed, and thus, has been attracting a great deal of attention as a potential beyond CMOS technology candidate for energy-efficient computing systems [2], [3]. Cryogenic rapid SFQ (RSFQ) circuits [4] have already reached a relative maturity realizing critical digital processing circuits [5]-[7] and producing integrated circuits of commercial significance [8]. Recently, SFQ technologies with even higher energy efficiency have been developed [9]-[14]. Still, a big leap is required for SFQ technologies to have integrated circuits reaching complexities and integration densities on par with the mature CMOS technology. A serious challenge for SFQ technologies is its relatively low integration density determined by the large geometries of superconducting quantum interferometer devices (SQUIDs) typical for SFQ circuits.
One of the most successful circuits in the semiconductor industry is field-programmable gate arrays (FPGAs) [15]. They are prefabricated CMOS circuits that can be electrically programmed on the field to become any circuit or system, as per the requirement of the user. Typically, FPGA is a cheaper and faster solution when compared to application specific integrated circuits, especially for the new circuit designs in the research and development phase [16]. Recently, a cryogenically cooled CMOS FPGA was used to implement a classical controller for quantum computing processors [17], [18] despite the dissipation a significant amount of power. The circuit energy efficiency is a priority for quantum computing applications requiring the cryogenic placement of FPGAs. Clearly, a superconducting energy-efficient FPGA would be an attractive option.
The first superconducting FPGA based on RSFQ logic was proposed in 2007 [19]. It relied on the implementation of switches based on a derivative of a non-destructive readout (NDRO) circuit controlled by dc bias to program the routing and the lookup tables (LUT) used to implement a configurable logic block in the FPGA fabric. The LUT-based configurable logic block could be programmed to implement any Boolean function of up to k inputs for a fixed and small value of k e.g., k=2. As a result, the total area used by switches occupied 65% of the total chip area. It also proposed the use of transformer coupling to control switches, which at a large scale can potentially cause yield and crosstalk issues. Recently, another superconducting FPGA was proposed [20] based on reciprocal quantum logic [12] and switchable phase shifters based on magnetic Josephson junctions (MJJs) embedded into dc SQUIDs. Although a complete operation or a detailed FPGA design was not elaborated, the use of SQUID-based switches and the combination of voltage-state (multi-SFQ) and SFQ signal regimes would make a future implementation of such FPGA challenging in achieving a high circuit density and energy efficiency.
Accordingly, there is a need for alternative and improved designs for FPGAs using superconducting components.